1. Field of the Invention
The present invention relates to a method for processing data of flash memory and flash memory device thereof, and more particularly to a method for processing data of flash memory by separating levels and flash memory device thereof.
2. Description of Related Art
Flash memory pertains to a non-violate solid state memory, and in contrast to the conventional non-violate solid state memory, it is advantageous in low unit storage cost and high read/write speed. Besides, flash memory has better shock resistance in comparison with a hard disk; in other words, the stored data therein is not easily damaged due to shock. For sake of the aforementioned nature, flash memory is often adopted in a portable device (e.g. MP3, digital camera, mobile phone, memory card and USB flash drive) as a storage medium.
Flash memory has many different types, for example, SLC (Single Level Cell) small block flash memory, SLC large block flash memory, MLC (Multi-Level Cell) large block flash memory, and so forth. Flash memory is made by various manufacturers, such as Samsung, Hynix, Toshiba, and so forth. Different types of flash memories or flash memories from different vendors have different structures and different control methods. For example, each block of the SLC small block flash memory contains 32 pages, and each page contains 528 bytes, in which the leading 512 bytes and the trailing 16 bytes are categorized as the data area and the spare area respectively, while each block of the SLC large block flash memory contains 64 pages, and each page contains 2112 bytes, in which the leading 2048 bytes and the trailing 64 bytes are categorized as the data area and the spare area respectively.
Please refer to FIG. 1, which is a schematic view illustrating a flash translation layer (FTL) of prior art. The FTL is electronically connected between a host H and a flash memory MF1.
The flash memory MF1 includes M×N blocks (BL11˜BLMN). The FTL is used to receive or respond to the request from the host H so as to process the data in the flash memory MF1. Moreover, the host can be an application program and/or a filing system over a user end.
The FTL reads hardware structure information DSPEC in the flash memory MF1. More specifically, the FTL reads the model number IDFLASH of the flash memory MF1 to acquire the type (e.g. SLC large block), manufacturer (e.g. Samsung), structure (e.g. size of block), capacity, control method, and so forth of the flash memory MF1 The FTL, in accordance with the structure of the flash memory MF1 described in the hardware structure information DSPEC, converts a logical address into a physical address corresponding to a physical storage unit of the flash memory MF1, and then identifies the control method corresponding to the flash memory MF1 to control the flash memory MF1 for data processing, so that the host H can request the flash memory MF1 through the FTL to perform a data processing operation. As an example, when the host H issues a request to the flash memory MF1 to perform a data processing operation and transmits a logical address “P” (representing a value) to the FTL, the FTL converts the logical address “P” into a physical address “X” and request to perform the data processing operation in the block BLX of the flash memory MF1.
What worth mentioning is that the FTL is required to directly control the flash memory MF1, and as a result, the FTL needs to be designed according to the control method and structure of the flash memory MF1. However, flash memories from different manufacturers or different types of flash memories own different control methods and structures. In that sense, whenever a flash memory MF1 (e.g. flash memory produced by Samsung) is replaced by a new flash memory MF2 (e.g. flash memory produced by Toshiba), the FTL needs to be re-designed in accordance with the control method and structure of the new flash memory MF2, thus giving rise to tremendous inconvenience to user.
To overcome the shortcomings, the present invention provides a method for processing data of flash memory by separating levels and flash memory device thereof to mitigate or obviate the aforementioned problems.